// system_qsys.v

// Generated using ACDS version 18.0 614

`timescale 1 ps / 1 ps
module system_qsys (
		output wire [7:0] avalon_segled_export_seg, // avalon_segled.export_seg
		output wire [5:0] avalon_segled_export_sel, //              .export_sel
		input  wire       clk_clk,                  //           clk.clk
		output wire       epcs_dclk,                //          epcs.dclk
		output wire       epcs_sce,                 //              .sce
		output wire       epcs_sdo,                 //              .sdo
		input  wire       epcs_data0,               //              .data0
		output wire       pio_beep_export,          //      pio_beep.export
		input  wire       pio_control_export,       //   pio_control.export
		input  wire       pio_down_export,          //      pio_down.export
		input  wire       pio_up_export,            //        pio_up.export
		input  wire       reset_reset_n             //         reset.reset_n
	);

	wire  [31:0] nios2_gen2_data_master_readdata;                                      // mm_interconnect_0:nios2_gen2_data_master_readdata -> nios2_gen2:d_readdata
	wire         nios2_gen2_data_master_waitrequest;                                   // mm_interconnect_0:nios2_gen2_data_master_waitrequest -> nios2_gen2:d_waitrequest
	wire         nios2_gen2_data_master_debugaccess;                                   // nios2_gen2:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:nios2_gen2_data_master_debugaccess
	wire  [15:0] nios2_gen2_data_master_address;                                       // nios2_gen2:d_address -> mm_interconnect_0:nios2_gen2_data_master_address
	wire   [3:0] nios2_gen2_data_master_byteenable;                                    // nios2_gen2:d_byteenable -> mm_interconnect_0:nios2_gen2_data_master_byteenable
	wire         nios2_gen2_data_master_read;                                          // nios2_gen2:d_read -> mm_interconnect_0:nios2_gen2_data_master_read
	wire         nios2_gen2_data_master_readdatavalid;                                 // mm_interconnect_0:nios2_gen2_data_master_readdatavalid -> nios2_gen2:d_readdatavalid
	wire         nios2_gen2_data_master_write;                                         // nios2_gen2:d_write -> mm_interconnect_0:nios2_gen2_data_master_write
	wire  [31:0] nios2_gen2_data_master_writedata;                                     // nios2_gen2:d_writedata -> mm_interconnect_0:nios2_gen2_data_master_writedata
	wire  [31:0] nios2_gen2_instruction_master_readdata;                               // mm_interconnect_0:nios2_gen2_instruction_master_readdata -> nios2_gen2:i_readdata
	wire         nios2_gen2_instruction_master_waitrequest;                            // mm_interconnect_0:nios2_gen2_instruction_master_waitrequest -> nios2_gen2:i_waitrequest
	wire  [15:0] nios2_gen2_instruction_master_address;                                // nios2_gen2:i_address -> mm_interconnect_0:nios2_gen2_instruction_master_address
	wire         nios2_gen2_instruction_master_read;                                   // nios2_gen2:i_read -> mm_interconnect_0:nios2_gen2_instruction_master_read
	wire         nios2_gen2_instruction_master_readdatavalid;                          // mm_interconnect_0:nios2_gen2_instruction_master_readdatavalid -> nios2_gen2:i_readdatavalid
	wire   [1:0] mm_interconnect_0_avalon_dtube_0_as_address;                          // mm_interconnect_0:avalon_dtube_0_as_address -> avalon_dtube_0:as_address
	wire         mm_interconnect_0_avalon_dtube_0_as_write;                            // mm_interconnect_0:avalon_dtube_0_as_write -> avalon_dtube_0:as_write
	wire  [31:0] mm_interconnect_0_avalon_dtube_0_as_writedata;                        // mm_interconnect_0:avalon_dtube_0_as_writedata -> avalon_dtube_0:as_writedata
	wire         mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect;             // mm_interconnect_0:jtag_uart_avalon_jtag_slave_chipselect -> jtag_uart:av_chipselect
	wire  [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata;               // jtag_uart:av_readdata -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_readdata
	wire         mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest;            // jtag_uart:av_waitrequest -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_waitrequest
	wire   [0:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_address;                // mm_interconnect_0:jtag_uart_avalon_jtag_slave_address -> jtag_uart:av_address
	wire         mm_interconnect_0_jtag_uart_avalon_jtag_slave_read;                   // mm_interconnect_0:jtag_uart_avalon_jtag_slave_read -> jtag_uart:av_read_n
	wire         mm_interconnect_0_jtag_uart_avalon_jtag_slave_write;                  // mm_interconnect_0:jtag_uart_avalon_jtag_slave_write -> jtag_uart:av_write_n
	wire  [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata;              // mm_interconnect_0:jtag_uart_avalon_jtag_slave_writedata -> jtag_uart:av_writedata
	wire  [31:0] mm_interconnect_0_sysid_qsys_control_slave_readdata;                  // sysid_qsys:readdata -> mm_interconnect_0:sysid_qsys_control_slave_readdata
	wire   [0:0] mm_interconnect_0_sysid_qsys_control_slave_address;                   // mm_interconnect_0:sysid_qsys_control_slave_address -> sysid_qsys:address
	wire  [31:0] mm_interconnect_0_nios2_gen2_debug_mem_slave_readdata;                // nios2_gen2:debug_mem_slave_readdata -> mm_interconnect_0:nios2_gen2_debug_mem_slave_readdata
	wire         mm_interconnect_0_nios2_gen2_debug_mem_slave_waitrequest;             // nios2_gen2:debug_mem_slave_waitrequest -> mm_interconnect_0:nios2_gen2_debug_mem_slave_waitrequest
	wire         mm_interconnect_0_nios2_gen2_debug_mem_slave_debugaccess;             // mm_interconnect_0:nios2_gen2_debug_mem_slave_debugaccess -> nios2_gen2:debug_mem_slave_debugaccess
	wire   [8:0] mm_interconnect_0_nios2_gen2_debug_mem_slave_address;                 // mm_interconnect_0:nios2_gen2_debug_mem_slave_address -> nios2_gen2:debug_mem_slave_address
	wire         mm_interconnect_0_nios2_gen2_debug_mem_slave_read;                    // mm_interconnect_0:nios2_gen2_debug_mem_slave_read -> nios2_gen2:debug_mem_slave_read
	wire   [3:0] mm_interconnect_0_nios2_gen2_debug_mem_slave_byteenable;              // mm_interconnect_0:nios2_gen2_debug_mem_slave_byteenable -> nios2_gen2:debug_mem_slave_byteenable
	wire         mm_interconnect_0_nios2_gen2_debug_mem_slave_write;                   // mm_interconnect_0:nios2_gen2_debug_mem_slave_write -> nios2_gen2:debug_mem_slave_write
	wire  [31:0] mm_interconnect_0_nios2_gen2_debug_mem_slave_writedata;               // mm_interconnect_0:nios2_gen2_debug_mem_slave_writedata -> nios2_gen2:debug_mem_slave_writedata
	wire         mm_interconnect_0_epcs_flash_controller_epcs_control_port_chipselect; // mm_interconnect_0:epcs_flash_controller_epcs_control_port_chipselect -> epcs_flash_controller:chipselect
	wire  [31:0] mm_interconnect_0_epcs_flash_controller_epcs_control_port_readdata;   // epcs_flash_controller:readdata -> mm_interconnect_0:epcs_flash_controller_epcs_control_port_readdata
	wire   [8:0] mm_interconnect_0_epcs_flash_controller_epcs_control_port_address;    // mm_interconnect_0:epcs_flash_controller_epcs_control_port_address -> epcs_flash_controller:address
	wire         mm_interconnect_0_epcs_flash_controller_epcs_control_port_read;       // mm_interconnect_0:epcs_flash_controller_epcs_control_port_read -> epcs_flash_controller:read_n
	wire         mm_interconnect_0_epcs_flash_controller_epcs_control_port_write;      // mm_interconnect_0:epcs_flash_controller_epcs_control_port_write -> epcs_flash_controller:write_n
	wire  [31:0] mm_interconnect_0_epcs_flash_controller_epcs_control_port_writedata;  // mm_interconnect_0:epcs_flash_controller_epcs_control_port_writedata -> epcs_flash_controller:writedata
	wire         mm_interconnect_0_onchip_ram_s1_chipselect;                           // mm_interconnect_0:onchip_ram_s1_chipselect -> onchip_ram:chipselect
	wire  [31:0] mm_interconnect_0_onchip_ram_s1_readdata;                             // onchip_ram:readdata -> mm_interconnect_0:onchip_ram_s1_readdata
	wire  [11:0] mm_interconnect_0_onchip_ram_s1_address;                              // mm_interconnect_0:onchip_ram_s1_address -> onchip_ram:address
	wire   [3:0] mm_interconnect_0_onchip_ram_s1_byteenable;                           // mm_interconnect_0:onchip_ram_s1_byteenable -> onchip_ram:byteenable
	wire         mm_interconnect_0_onchip_ram_s1_write;                                // mm_interconnect_0:onchip_ram_s1_write -> onchip_ram:write
	wire  [31:0] mm_interconnect_0_onchip_ram_s1_writedata;                            // mm_interconnect_0:onchip_ram_s1_writedata -> onchip_ram:writedata
	wire         mm_interconnect_0_onchip_ram_s1_clken;                                // mm_interconnect_0:onchip_ram_s1_clken -> onchip_ram:clken
	wire         mm_interconnect_0_timer_s1_chipselect;                                // mm_interconnect_0:timer_s1_chipselect -> timer:chipselect
	wire  [15:0] mm_interconnect_0_timer_s1_readdata;                                  // timer:readdata -> mm_interconnect_0:timer_s1_readdata
	wire   [2:0] mm_interconnect_0_timer_s1_address;                                   // mm_interconnect_0:timer_s1_address -> timer:address
	wire         mm_interconnect_0_timer_s1_write;                                     // mm_interconnect_0:timer_s1_write -> timer:write_n
	wire  [15:0] mm_interconnect_0_timer_s1_writedata;                                 // mm_interconnect_0:timer_s1_writedata -> timer:writedata
	wire         mm_interconnect_0_pio_beep_s1_chipselect;                             // mm_interconnect_0:pio_beep_s1_chipselect -> pio_beep:chipselect
	wire  [31:0] mm_interconnect_0_pio_beep_s1_readdata;                               // pio_beep:readdata -> mm_interconnect_0:pio_beep_s1_readdata
	wire   [1:0] mm_interconnect_0_pio_beep_s1_address;                                // mm_interconnect_0:pio_beep_s1_address -> pio_beep:address
	wire         mm_interconnect_0_pio_beep_s1_write;                                  // mm_interconnect_0:pio_beep_s1_write -> pio_beep:write_n
	wire  [31:0] mm_interconnect_0_pio_beep_s1_writedata;                              // mm_interconnect_0:pio_beep_s1_writedata -> pio_beep:writedata
	wire         mm_interconnect_0_pio_control_s1_chipselect;                          // mm_interconnect_0:pio_control_s1_chipselect -> pio_control:chipselect
	wire  [31:0] mm_interconnect_0_pio_control_s1_readdata;                            // pio_control:readdata -> mm_interconnect_0:pio_control_s1_readdata
	wire   [1:0] mm_interconnect_0_pio_control_s1_address;                             // mm_interconnect_0:pio_control_s1_address -> pio_control:address
	wire         mm_interconnect_0_pio_control_s1_write;                               // mm_interconnect_0:pio_control_s1_write -> pio_control:write_n
	wire  [31:0] mm_interconnect_0_pio_control_s1_writedata;                           // mm_interconnect_0:pio_control_s1_writedata -> pio_control:writedata
	wire         mm_interconnect_0_pio_up_s1_chipselect;                               // mm_interconnect_0:pio_up_s1_chipselect -> pio_up:chipselect
	wire  [31:0] mm_interconnect_0_pio_up_s1_readdata;                                 // pio_up:readdata -> mm_interconnect_0:pio_up_s1_readdata
	wire   [1:0] mm_interconnect_0_pio_up_s1_address;                                  // mm_interconnect_0:pio_up_s1_address -> pio_up:address
	wire         mm_interconnect_0_pio_up_s1_write;                                    // mm_interconnect_0:pio_up_s1_write -> pio_up:write_n
	wire  [31:0] mm_interconnect_0_pio_up_s1_writedata;                                // mm_interconnect_0:pio_up_s1_writedata -> pio_up:writedata
	wire         mm_interconnect_0_pio_down_s1_chipselect;                             // mm_interconnect_0:pio_down_s1_chipselect -> pio_down:chipselect
	wire  [31:0] mm_interconnect_0_pio_down_s1_readdata;                               // pio_down:readdata -> mm_interconnect_0:pio_down_s1_readdata
	wire   [1:0] mm_interconnect_0_pio_down_s1_address;                                // mm_interconnect_0:pio_down_s1_address -> pio_down:address
	wire         mm_interconnect_0_pio_down_s1_write;                                  // mm_interconnect_0:pio_down_s1_write -> pio_down:write_n
	wire  [31:0] mm_interconnect_0_pio_down_s1_writedata;                              // mm_interconnect_0:pio_down_s1_writedata -> pio_down:writedata
	wire         irq_mapper_receiver0_irq;                                             // epcs_flash_controller:irq -> irq_mapper:receiver0_irq
	wire         irq_mapper_receiver1_irq;                                             // jtag_uart:av_irq -> irq_mapper:receiver1_irq
	wire         irq_mapper_receiver2_irq;                                             // timer:irq -> irq_mapper:receiver2_irq
	wire         irq_mapper_receiver3_irq;                                             // pio_control:irq -> irq_mapper:receiver3_irq
	wire         irq_mapper_receiver4_irq;                                             // pio_up:irq -> irq_mapper:receiver4_irq
	wire         irq_mapper_receiver5_irq;                                             // pio_down:irq -> irq_mapper:receiver5_irq
	wire  [31:0] nios2_gen2_irq_irq;                                                   // irq_mapper:sender_irq -> nios2_gen2:irq
	wire         rst_controller_reset_out_reset;                                       // rst_controller:reset_out -> [avalon_dtube_0:reset, epcs_flash_controller:reset_n, irq_mapper:reset, jtag_uart:rst_n, mm_interconnect_0:nios2_gen2_reset_reset_bridge_in_reset_reset, nios2_gen2:reset_n, onchip_ram:reset, pio_beep:reset_n, pio_control:reset_n, pio_down:reset_n, pio_up:reset_n, rst_translator:in_reset, sysid_qsys:reset_n, timer:reset_n]
	wire         rst_controller_reset_out_reset_req;                                   // rst_controller:reset_req -> [epcs_flash_controller:reset_req, nios2_gen2:reset_req, onchip_ram:reset_req, rst_translator:reset_req_in]
	wire         nios2_gen2_debug_reset_request_reset;                                 // nios2_gen2:debug_reset_request -> rst_controller:reset_in1

	avalon_dtube avalon_dtube_0 (
		.clk          (clk_clk),                                       //       clock.clk
		.reset        (~rst_controller_reset_out_reset),               //       reset.reset_n
		.as_address   (mm_interconnect_0_avalon_dtube_0_as_address),   //          as.address
		.as_write     (mm_interconnect_0_avalon_dtube_0_as_write),     //            .write
		.as_writedata (mm_interconnect_0_avalon_dtube_0_as_writedata), //            .writedata
		.data_seg     (avalon_segled_export_seg),                      // conduit_end.export_seg
		.data_sel     (avalon_segled_export_sel)                       //            .export_sel
	);

	system_qsys_epcs_flash_controller epcs_flash_controller (
		.clk        (clk_clk),                                                              //               clk.clk
		.reset_n    (~rst_controller_reset_out_reset),                                      //             reset.reset_n
		.reset_req  (rst_controller_reset_out_reset_req),                                   //                  .reset_req
		.address    (mm_interconnect_0_epcs_flash_controller_epcs_control_port_address),    // epcs_control_port.address
		.chipselect (mm_interconnect_0_epcs_flash_controller_epcs_control_port_chipselect), //                  .chipselect
		.read_n     (~mm_interconnect_0_epcs_flash_controller_epcs_control_port_read),      //                  .read_n
		.readdata   (mm_interconnect_0_epcs_flash_controller_epcs_control_port_readdata),   //                  .readdata
		.write_n    (~mm_interconnect_0_epcs_flash_controller_epcs_control_port_write),     //                  .write_n
		.writedata  (mm_interconnect_0_epcs_flash_controller_epcs_control_port_writedata),  //                  .writedata
		.irq        (irq_mapper_receiver0_irq),                                             //               irq.irq
		.dclk       (epcs_dclk),                                                            //          external.export
		.sce        (epcs_sce),                                                             //                  .export
		.sdo        (epcs_sdo),                                                             //                  .export
		.data0      (epcs_data0)                                                            //                  .export
	);

	system_qsys_jtag_uart jtag_uart (
		.clk            (clk_clk),                                                   //               clk.clk
		.rst_n          (~rst_controller_reset_out_reset),                           //             reset.reset_n
		.av_chipselect  (mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect),  // avalon_jtag_slave.chipselect
		.av_address     (mm_interconnect_0_jtag_uart_avalon_jtag_slave_address),     //                  .address
		.av_read_n      (~mm_interconnect_0_jtag_uart_avalon_jtag_slave_read),       //                  .read_n
		.av_readdata    (mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata),    //                  .readdata
		.av_write_n     (~mm_interconnect_0_jtag_uart_avalon_jtag_slave_write),      //                  .write_n
		.av_writedata   (mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata),   //                  .writedata
		.av_waitrequest (mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest), //                  .waitrequest
		.av_irq         (irq_mapper_receiver1_irq)                                   //               irq.irq
	);

	system_qsys_nios2_gen2 nios2_gen2 (
		.clk                                 (clk_clk),                                                  //                       clk.clk
		.reset_n                             (~rst_controller_reset_out_reset),                          //                     reset.reset_n
		.reset_req                           (rst_controller_reset_out_reset_req),                       //                          .reset_req
		.d_address                           (nios2_gen2_data_master_address),                           //               data_master.address
		.d_byteenable                        (nios2_gen2_data_master_byteenable),                        //                          .byteenable
		.d_read                              (nios2_gen2_data_master_read),                              //                          .read
		.d_readdata                          (nios2_gen2_data_master_readdata),                          //                          .readdata
		.d_waitrequest                       (nios2_gen2_data_master_waitrequest),                       //                          .waitrequest
		.d_write                             (nios2_gen2_data_master_write),                             //                          .write
		.d_writedata                         (nios2_gen2_data_master_writedata),                         //                          .writedata
		.d_readdatavalid                     (nios2_gen2_data_master_readdatavalid),                     //                          .readdatavalid
		.debug_mem_slave_debugaccess_to_roms (nios2_gen2_data_master_debugaccess),                       //                          .debugaccess
		.i_address                           (nios2_gen2_instruction_master_address),                    //        instruction_master.address
		.i_read                              (nios2_gen2_instruction_master_read),                       //                          .read
		.i_readdata                          (nios2_gen2_instruction_master_readdata),                   //                          .readdata
		.i_waitrequest                       (nios2_gen2_instruction_master_waitrequest),                //                          .waitrequest
		.i_readdatavalid                     (nios2_gen2_instruction_master_readdatavalid),              //                          .readdatavalid
		.irq                                 (nios2_gen2_irq_irq),                                       //                       irq.irq
		.debug_reset_request                 (nios2_gen2_debug_reset_request_reset),                     //       debug_reset_request.reset
		.debug_mem_slave_address             (mm_interconnect_0_nios2_gen2_debug_mem_slave_address),     //           debug_mem_slave.address
		.debug_mem_slave_byteenable          (mm_interconnect_0_nios2_gen2_debug_mem_slave_byteenable),  //                          .byteenable
		.debug_mem_slave_debugaccess         (mm_interconnect_0_nios2_gen2_debug_mem_slave_debugaccess), //                          .debugaccess
		.debug_mem_slave_read                (mm_interconnect_0_nios2_gen2_debug_mem_slave_read),        //                          .read
		.debug_mem_slave_readdata            (mm_interconnect_0_nios2_gen2_debug_mem_slave_readdata),    //                          .readdata
		.debug_mem_slave_waitrequest         (mm_interconnect_0_nios2_gen2_debug_mem_slave_waitrequest), //                          .waitrequest
		.debug_mem_slave_write               (mm_interconnect_0_nios2_gen2_debug_mem_slave_write),       //                          .write
		.debug_mem_slave_writedata           (mm_interconnect_0_nios2_gen2_debug_mem_slave_writedata),   //                          .writedata
		.dummy_ci_port                       ()                                                          // custom_instruction_master.readra
	);

	system_qsys_onchip_ram onchip_ram (
		.clk        (clk_clk),                                    //   clk1.clk
		.address    (mm_interconnect_0_onchip_ram_s1_address),    //     s1.address
		.clken      (mm_interconnect_0_onchip_ram_s1_clken),      //       .clken
		.chipselect (mm_interconnect_0_onchip_ram_s1_chipselect), //       .chipselect
		.write      (mm_interconnect_0_onchip_ram_s1_write),      //       .write
		.readdata   (mm_interconnect_0_onchip_ram_s1_readdata),   //       .readdata
		.writedata  (mm_interconnect_0_onchip_ram_s1_writedata),  //       .writedata
		.byteenable (mm_interconnect_0_onchip_ram_s1_byteenable), //       .byteenable
		.reset      (rst_controller_reset_out_reset),             // reset1.reset
		.reset_req  (rst_controller_reset_out_reset_req),         //       .reset_req
		.freeze     (1'b0)                                        // (terminated)
	);

	system_qsys_pio_beep pio_beep (
		.clk        (clk_clk),                                  //                 clk.clk
		.reset_n    (~rst_controller_reset_out_reset),          //               reset.reset_n
		.address    (mm_interconnect_0_pio_beep_s1_address),    //                  s1.address
		.write_n    (~mm_interconnect_0_pio_beep_s1_write),     //                    .write_n
		.writedata  (mm_interconnect_0_pio_beep_s1_writedata),  //                    .writedata
		.chipselect (mm_interconnect_0_pio_beep_s1_chipselect), //                    .chipselect
		.readdata   (mm_interconnect_0_pio_beep_s1_readdata),   //                    .readdata
		.out_port   (pio_beep_export)                           // external_connection.export
	);

	system_qsys_pio_control pio_control (
		.clk        (clk_clk),                                     //                 clk.clk
		.reset_n    (~rst_controller_reset_out_reset),             //               reset.reset_n
		.address    (mm_interconnect_0_pio_control_s1_address),    //                  s1.address
		.write_n    (~mm_interconnect_0_pio_control_s1_write),     //                    .write_n
		.writedata  (mm_interconnect_0_pio_control_s1_writedata),  //                    .writedata
		.chipselect (mm_interconnect_0_pio_control_s1_chipselect), //                    .chipselect
		.readdata   (mm_interconnect_0_pio_control_s1_readdata),   //                    .readdata
		.in_port    (pio_control_export),                          // external_connection.export
		.irq        (irq_mapper_receiver3_irq)                     //                 irq.irq
	);

	system_qsys_pio_control pio_down (
		.clk        (clk_clk),                                  //                 clk.clk
		.reset_n    (~rst_controller_reset_out_reset),          //               reset.reset_n
		.address    (mm_interconnect_0_pio_down_s1_address),    //                  s1.address
		.write_n    (~mm_interconnect_0_pio_down_s1_write),     //                    .write_n
		.writedata  (mm_interconnect_0_pio_down_s1_writedata),  //                    .writedata
		.chipselect (mm_interconnect_0_pio_down_s1_chipselect), //                    .chipselect
		.readdata   (mm_interconnect_0_pio_down_s1_readdata),   //                    .readdata
		.in_port    (pio_down_export),                          // external_connection.export
		.irq        (irq_mapper_receiver5_irq)                  //                 irq.irq
	);

	system_qsys_pio_control pio_up (
		.clk        (clk_clk),                                //                 clk.clk
		.reset_n    (~rst_controller_reset_out_reset),        //               reset.reset_n
		.address    (mm_interconnect_0_pio_up_s1_address),    //                  s1.address
		.write_n    (~mm_interconnect_0_pio_up_s1_write),     //                    .write_n
		.writedata  (mm_interconnect_0_pio_up_s1_writedata),  //                    .writedata
		.chipselect (mm_interconnect_0_pio_up_s1_chipselect), //                    .chipselect
		.readdata   (mm_interconnect_0_pio_up_s1_readdata),   //                    .readdata
		.in_port    (pio_up_export),                          // external_connection.export
		.irq        (irq_mapper_receiver4_irq)                //                 irq.irq
	);

	system_qsys_sysid_qsys sysid_qsys (
		.clock    (clk_clk),                                             //           clk.clk
		.reset_n  (~rst_controller_reset_out_reset),                     //         reset.reset_n
		.readdata (mm_interconnect_0_sysid_qsys_control_slave_readdata), // control_slave.readdata
		.address  (mm_interconnect_0_sysid_qsys_control_slave_address)   //              .address
	);

	system_qsys_timer timer (
		.clk        (clk_clk),                               //   clk.clk
		.reset_n    (~rst_controller_reset_out_reset),       // reset.reset_n
		.address    (mm_interconnect_0_timer_s1_address),    //    s1.address
		.writedata  (mm_interconnect_0_timer_s1_writedata),  //      .writedata
		.readdata   (mm_interconnect_0_timer_s1_readdata),   //      .readdata
		.chipselect (mm_interconnect_0_timer_s1_chipselect), //      .chipselect
		.write_n    (~mm_interconnect_0_timer_s1_write),     //      .write_n
		.irq        (irq_mapper_receiver2_irq)               //   irq.irq
	);

	system_qsys_mm_interconnect_0 mm_interconnect_0 (
		.clk_0_clk_clk                                      (clk_clk),                                                              //                               clk_0_clk.clk
		.nios2_gen2_reset_reset_bridge_in_reset_reset       (rst_controller_reset_out_reset),                                       //  nios2_gen2_reset_reset_bridge_in_reset.reset
		.nios2_gen2_data_master_address                     (nios2_gen2_data_master_address),                                       //                  nios2_gen2_data_master.address
		.nios2_gen2_data_master_waitrequest                 (nios2_gen2_data_master_waitrequest),                                   //                                        .waitrequest
		.nios2_gen2_data_master_byteenable                  (nios2_gen2_data_master_byteenable),                                    //                                        .byteenable
		.nios2_gen2_data_master_read                        (nios2_gen2_data_master_read),                                          //                                        .read
		.nios2_gen2_data_master_readdata                    (nios2_gen2_data_master_readdata),                                      //                                        .readdata
		.nios2_gen2_data_master_readdatavalid               (nios2_gen2_data_master_readdatavalid),                                 //                                        .readdatavalid
		.nios2_gen2_data_master_write                       (nios2_gen2_data_master_write),                                         //                                        .write
		.nios2_gen2_data_master_writedata                   (nios2_gen2_data_master_writedata),                                     //                                        .writedata
		.nios2_gen2_data_master_debugaccess                 (nios2_gen2_data_master_debugaccess),                                   //                                        .debugaccess
		.nios2_gen2_instruction_master_address              (nios2_gen2_instruction_master_address),                                //           nios2_gen2_instruction_master.address
		.nios2_gen2_instruction_master_waitrequest          (nios2_gen2_instruction_master_waitrequest),                            //                                        .waitrequest
		.nios2_gen2_instruction_master_read                 (nios2_gen2_instruction_master_read),                                   //                                        .read
		.nios2_gen2_instruction_master_readdata             (nios2_gen2_instruction_master_readdata),                               //                                        .readdata
		.nios2_gen2_instruction_master_readdatavalid        (nios2_gen2_instruction_master_readdatavalid),                          //                                        .readdatavalid
		.avalon_dtube_0_as_address                          (mm_interconnect_0_avalon_dtube_0_as_address),                          //                       avalon_dtube_0_as.address
		.avalon_dtube_0_as_write                            (mm_interconnect_0_avalon_dtube_0_as_write),                            //                                        .write
		.avalon_dtube_0_as_writedata                        (mm_interconnect_0_avalon_dtube_0_as_writedata),                        //                                        .writedata
		.epcs_flash_controller_epcs_control_port_address    (mm_interconnect_0_epcs_flash_controller_epcs_control_port_address),    // epcs_flash_controller_epcs_control_port.address
		.epcs_flash_controller_epcs_control_port_write      (mm_interconnect_0_epcs_flash_controller_epcs_control_port_write),      //                                        .write
		.epcs_flash_controller_epcs_control_port_read       (mm_interconnect_0_epcs_flash_controller_epcs_control_port_read),       //                                        .read
		.epcs_flash_controller_epcs_control_port_readdata   (mm_interconnect_0_epcs_flash_controller_epcs_control_port_readdata),   //                                        .readdata
		.epcs_flash_controller_epcs_control_port_writedata  (mm_interconnect_0_epcs_flash_controller_epcs_control_port_writedata),  //                                        .writedata
		.epcs_flash_controller_epcs_control_port_chipselect (mm_interconnect_0_epcs_flash_controller_epcs_control_port_chipselect), //                                        .chipselect
		.jtag_uart_avalon_jtag_slave_address                (mm_interconnect_0_jtag_uart_avalon_jtag_slave_address),                //             jtag_uart_avalon_jtag_slave.address
		.jtag_uart_avalon_jtag_slave_write                  (mm_interconnect_0_jtag_uart_avalon_jtag_slave_write),                  //                                        .write
		.jtag_uart_avalon_jtag_slave_read                   (mm_interconnect_0_jtag_uart_avalon_jtag_slave_read),                   //                                        .read
		.jtag_uart_avalon_jtag_slave_readdata               (mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata),               //                                        .readdata
		.jtag_uart_avalon_jtag_slave_writedata              (mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata),              //                                        .writedata
		.jtag_uart_avalon_jtag_slave_waitrequest            (mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest),            //                                        .waitrequest
		.jtag_uart_avalon_jtag_slave_chipselect             (mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect),             //                                        .chipselect
		.nios2_gen2_debug_mem_slave_address                 (mm_interconnect_0_nios2_gen2_debug_mem_slave_address),                 //              nios2_gen2_debug_mem_slave.address
		.nios2_gen2_debug_mem_slave_write                   (mm_interconnect_0_nios2_gen2_debug_mem_slave_write),                   //                                        .write
		.nios2_gen2_debug_mem_slave_read                    (mm_interconnect_0_nios2_gen2_debug_mem_slave_read),                    //                                        .read
		.nios2_gen2_debug_mem_slave_readdata                (mm_interconnect_0_nios2_gen2_debug_mem_slave_readdata),                //                                        .readdata
		.nios2_gen2_debug_mem_slave_writedata               (mm_interconnect_0_nios2_gen2_debug_mem_slave_writedata),               //                                        .writedata
		.nios2_gen2_debug_mem_slave_byteenable              (mm_interconnect_0_nios2_gen2_debug_mem_slave_byteenable),              //                                        .byteenable
		.nios2_gen2_debug_mem_slave_waitrequest             (mm_interconnect_0_nios2_gen2_debug_mem_slave_waitrequest),             //                                        .waitrequest
		.nios2_gen2_debug_mem_slave_debugaccess             (mm_interconnect_0_nios2_gen2_debug_mem_slave_debugaccess),             //                                        .debugaccess
		.onchip_ram_s1_address                              (mm_interconnect_0_onchip_ram_s1_address),                              //                           onchip_ram_s1.address
		.onchip_ram_s1_write                                (mm_interconnect_0_onchip_ram_s1_write),                                //                                        .write
		.onchip_ram_s1_readdata                             (mm_interconnect_0_onchip_ram_s1_readdata),                             //                                        .readdata
		.onchip_ram_s1_writedata                            (mm_interconnect_0_onchip_ram_s1_writedata),                            //                                        .writedata
		.onchip_ram_s1_byteenable                           (mm_interconnect_0_onchip_ram_s1_byteenable),                           //                                        .byteenable
		.onchip_ram_s1_chipselect                           (mm_interconnect_0_onchip_ram_s1_chipselect),                           //                                        .chipselect
		.onchip_ram_s1_clken                                (mm_interconnect_0_onchip_ram_s1_clken),                                //                                        .clken
		.pio_beep_s1_address                                (mm_interconnect_0_pio_beep_s1_address),                                //                             pio_beep_s1.address
		.pio_beep_s1_write                                  (mm_interconnect_0_pio_beep_s1_write),                                  //                                        .write
		.pio_beep_s1_readdata                               (mm_interconnect_0_pio_beep_s1_readdata),                               //                                        .readdata
		.pio_beep_s1_writedata                              (mm_interconnect_0_pio_beep_s1_writedata),                              //                                        .writedata
		.pio_beep_s1_chipselect                             (mm_interconnect_0_pio_beep_s1_chipselect),                             //                                        .chipselect
		.pio_control_s1_address                             (mm_interconnect_0_pio_control_s1_address),                             //                          pio_control_s1.address
		.pio_control_s1_write                               (mm_interconnect_0_pio_control_s1_write),                               //                                        .write
		.pio_control_s1_readdata                            (mm_interconnect_0_pio_control_s1_readdata),                            //                                        .readdata
		.pio_control_s1_writedata                           (mm_interconnect_0_pio_control_s1_writedata),                           //                                        .writedata
		.pio_control_s1_chipselect                          (mm_interconnect_0_pio_control_s1_chipselect),                          //                                        .chipselect
		.pio_down_s1_address                                (mm_interconnect_0_pio_down_s1_address),                                //                             pio_down_s1.address
		.pio_down_s1_write                                  (mm_interconnect_0_pio_down_s1_write),                                  //                                        .write
		.pio_down_s1_readdata                               (mm_interconnect_0_pio_down_s1_readdata),                               //                                        .readdata
		.pio_down_s1_writedata                              (mm_interconnect_0_pio_down_s1_writedata),                              //                                        .writedata
		.pio_down_s1_chipselect                             (mm_interconnect_0_pio_down_s1_chipselect),                             //                                        .chipselect
		.pio_up_s1_address                                  (mm_interconnect_0_pio_up_s1_address),                                  //                               pio_up_s1.address
		.pio_up_s1_write                                    (mm_interconnect_0_pio_up_s1_write),                                    //                                        .write
		.pio_up_s1_readdata                                 (mm_interconnect_0_pio_up_s1_readdata),                                 //                                        .readdata
		.pio_up_s1_writedata                                (mm_interconnect_0_pio_up_s1_writedata),                                //                                        .writedata
		.pio_up_s1_chipselect                               (mm_interconnect_0_pio_up_s1_chipselect),                               //                                        .chipselect
		.sysid_qsys_control_slave_address                   (mm_interconnect_0_sysid_qsys_control_slave_address),                   //                sysid_qsys_control_slave.address
		.sysid_qsys_control_slave_readdata                  (mm_interconnect_0_sysid_qsys_control_slave_readdata),                  //                                        .readdata
		.timer_s1_address                                   (mm_interconnect_0_timer_s1_address),                                   //                                timer_s1.address
		.timer_s1_write                                     (mm_interconnect_0_timer_s1_write),                                     //                                        .write
		.timer_s1_readdata                                  (mm_interconnect_0_timer_s1_readdata),                                  //                                        .readdata
		.timer_s1_writedata                                 (mm_interconnect_0_timer_s1_writedata),                                 //                                        .writedata
		.timer_s1_chipselect                                (mm_interconnect_0_timer_s1_chipselect)                                 //                                        .chipselect
	);

	system_qsys_irq_mapper irq_mapper (
		.clk           (clk_clk),                        //       clk.clk
		.reset         (rst_controller_reset_out_reset), // clk_reset.reset
		.receiver0_irq (irq_mapper_receiver0_irq),       // receiver0.irq
		.receiver1_irq (irq_mapper_receiver1_irq),       // receiver1.irq
		.receiver2_irq (irq_mapper_receiver2_irq),       // receiver2.irq
		.receiver3_irq (irq_mapper_receiver3_irq),       // receiver3.irq
		.receiver4_irq (irq_mapper_receiver4_irq),       // receiver4.irq
		.receiver5_irq (irq_mapper_receiver5_irq),       // receiver5.irq
		.sender_irq    (nios2_gen2_irq_irq)              //    sender.irq
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS          (2),
		.OUTPUT_RESET_SYNC_EDGES   ("deassert"),
		.SYNC_DEPTH                (2),
		.RESET_REQUEST_PRESENT     (1),
		.RESET_REQ_WAIT_TIME       (1),
		.MIN_RST_ASSERTION_TIME    (3),
		.RESET_REQ_EARLY_DSRT_TIME (1),
		.USE_RESET_REQUEST_IN0     (0),
		.USE_RESET_REQUEST_IN1     (0),
		.USE_RESET_REQUEST_IN2     (0),
		.USE_RESET_REQUEST_IN3     (0),
		.USE_RESET_REQUEST_IN4     (0),
		.USE_RESET_REQUEST_IN5     (0),
		.USE_RESET_REQUEST_IN6     (0),
		.USE_RESET_REQUEST_IN7     (0),
		.USE_RESET_REQUEST_IN8     (0),
		.USE_RESET_REQUEST_IN9     (0),
		.USE_RESET_REQUEST_IN10    (0),
		.USE_RESET_REQUEST_IN11    (0),
		.USE_RESET_REQUEST_IN12    (0),
		.USE_RESET_REQUEST_IN13    (0),
		.USE_RESET_REQUEST_IN14    (0),
		.USE_RESET_REQUEST_IN15    (0),
		.ADAPT_RESET_REQUEST       (0)
	) rst_controller (
		.reset_in0      (~reset_reset_n),                       // reset_in0.reset
		.reset_in1      (nios2_gen2_debug_reset_request_reset), // reset_in1.reset
		.clk            (clk_clk),                              //       clk.clk
		.reset_out      (rst_controller_reset_out_reset),       // reset_out.reset
		.reset_req      (rst_controller_reset_out_reset_req),   //          .reset_req
		.reset_req_in0  (1'b0),                                 // (terminated)
		.reset_req_in1  (1'b0),                                 // (terminated)
		.reset_in2      (1'b0),                                 // (terminated)
		.reset_req_in2  (1'b0),                                 // (terminated)
		.reset_in3      (1'b0),                                 // (terminated)
		.reset_req_in3  (1'b0),                                 // (terminated)
		.reset_in4      (1'b0),                                 // (terminated)
		.reset_req_in4  (1'b0),                                 // (terminated)
		.reset_in5      (1'b0),                                 // (terminated)
		.reset_req_in5  (1'b0),                                 // (terminated)
		.reset_in6      (1'b0),                                 // (terminated)
		.reset_req_in6  (1'b0),                                 // (terminated)
		.reset_in7      (1'b0),                                 // (terminated)
		.reset_req_in7  (1'b0),                                 // (terminated)
		.reset_in8      (1'b0),                                 // (terminated)
		.reset_req_in8  (1'b0),                                 // (terminated)
		.reset_in9      (1'b0),                                 // (terminated)
		.reset_req_in9  (1'b0),                                 // (terminated)
		.reset_in10     (1'b0),                                 // (terminated)
		.reset_req_in10 (1'b0),                                 // (terminated)
		.reset_in11     (1'b0),                                 // (terminated)
		.reset_req_in11 (1'b0),                                 // (terminated)
		.reset_in12     (1'b0),                                 // (terminated)
		.reset_req_in12 (1'b0),                                 // (terminated)
		.reset_in13     (1'b0),                                 // (terminated)
		.reset_req_in13 (1'b0),                                 // (terminated)
		.reset_in14     (1'b0),                                 // (terminated)
		.reset_req_in14 (1'b0),                                 // (terminated)
		.reset_in15     (1'b0),                                 // (terminated)
		.reset_req_in15 (1'b0)                                  // (terminated)
	);

endmodule
